Multi-chip packaging is a semiconductor packaging technology which stacks two or more semiconductor die with the same or different sizes in a single package. When packaging multiple semiconductor dice in a conventional multi-chip package where the semiconductor die sizes are different, the biggest die is placed on a substrate and the smaller die is placed on top of the larger die and attached thereto using adhesive. The contacts on the upper die are wirebonded to pads on the substrate. The pads for the upper die are necessarily located outside the footprint of the bottom die requiring that the substrate necessarily be larger than the largest die. Multi-chip packages can commonly be found in portable electronic devices such as cellular telephones and digital cameras. As these devices increase functionality and complexity while decreasing size, smaller semiconductor package sizes become a requirement. Conventional multi-chip packages provide space savings by packaging several die in a single package, but are constrained to be larger than the largest die in the package by sufficient area to locate contact pads for all the semiconductor dice in the package on the substrate outside the footprint of the largest die.
Accordingly, it is desirable to provide a method and apparatus for multi-chip packaging which retains the benefits of conventional multi-chip packages while allowing for reduction in the size of the packages. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.